An ASIC (Application Specific Integration Circuit) is almost any IC which is not a generic processor (CPU). It can be a full custom, COT product (Customer Owned Tooling where the IC designer supplies the GDS2 to the foundry) but it is usually used for Standard Cell based Designs. The sign-off can be at RTL, Static Timing Analyzed Gate Level or GDS2 level. The NRE goes down with each step (IOW, RTL sign-off NRE is higher than GDS2 NRE).
ASIC development usually consists of the following steps:
- RTL Design & Verification
- RTL is usually designed with either Verilog or VHDL Language
- There are many languages specifically designed to enhance Verification like E, Verisity etc.
- ASIC Synthesis is mainly done with Synopsys Design Compiler, Cadence (Ambit) Buildgates or one of the newer RTL to GDS2 tools like Magma or Monterey. Synopsys and Cadence also have RTL to GDS2 tools PKS etc.
- Currently Talus from Magma is our most favorite P&R tool. Its synthesis, placement and routing QOR are second to none.
- Placement. QPlace, Amoeba Placer are tools from Cadence
- Clock Tree Generation.
- CTGEN from Cadence is one tool which does Clock Tree Generation and Insertion. Also CTPKS is part of SOCE. Talus CTS is extremely good.
- BIST or Scan Insertion is part of DFT flow.
- Routing. Astro from Synopsys, NanoRoute from Cadence are good examples. Also Talus Router is extremely capable and fast.
- In Place Optimization (IPO).
- GDS2 generation.
- Layout Versus Schematic (LVS) & Design Rule Checking (DRC) of the Design file.
- Dracula has been the main DRC tool for a very long time. Now Mentor Calibre, Cadence Assura LVS & DRC are also popular among others.
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